Copyright © 2016–2017, Texas Instruments IncorporatedTerminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: AM5706 AM5708
30
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
www.ti.com
Table 4-1. Pin Attributes
(1)
(continued)
BALL NUMBER
[1]
BALL NAME [2] SIGNAL NAME [3] PN [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
RESET
REL.
STATE [8]
BALL
RESET
REL.
MUXMODE
[9]
I/O
VOLTAGE
VALUE
[10]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
DSIS [15]
E19 mcasp2_aclkx mcasp2_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual
Voltage
LVCMOS
PU/PD 0
vin1a_d7 7 I 0
pr2_mii0_rxd2 11 I 0
pr2_pru0_gpi18 12 I
pr2_pru0_gpo18 13 O
Driver off 15 I
D19 mcasp2_fsx mcasp2_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual
Voltage
LVCMOS
PU/PD 0
vin1a_d6 7 I 0
pr2_mii0_rxd1 11 I 0
pr2_pru0_gpi19 12 I
pr2_pru0_gpo19 13 O
Driver off 15 I
A22 mcasp3_aclkx mcasp3_aclkx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual
Voltage
LVCMOS
PU/PD 0
mcasp3_aclkr 1 IO
mcasp2_axr12 2 IO 0
uart7_rxd 3 I 1
vin1a_d3 7 I 0
pr2_mii0_crs 11 I 0
pr2_pru0_gpi12 12 I
pr2_pru0_gpo12 13 O
gpio5_13 14 IO
Driver off 15 I
A23 mcasp3_fsx mcasp3_fsx 0 IO PD PD 15 1.8/3.3 vddshv3 Yes Dual
Voltage
LVCMOS
PU/PD 0
mcasp3_fsr 1 IO
mcasp2_axr13 2 IO 0
uart7_txd 3 O
vin1a_d2 7 I 0
pr2_mii0_col 11 I 0
pr2_pru0_gpi13 12 I
pr2_pru0_gpo13 13 O
gpio5_14 14 IO
Driver off 15 I