MII_RXCLK
2
3
1
4
4
SPRS91x_TIMING_PRU_MII_RT_04
1
MDIO_CLK (Output)
MDIO_DATA (Output)
SPRS91x_TIMING_PRU_MII_RT_03
MDIO_CLK
2
3
1
4
4
SPRS91x_TIMING_PRU_MII_RT_02
296
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Specifications Copyright © 2016–2017, Texas Instruments Incorporated
Figure 5-118. PRU-ICSS MDIO_CLK Timing
Table 5-168. PRU-ICSS MDIO Switching Characteristics – MDIO_DATA
NO. PARAMETER DESCRIPTION MIN MAX UNIT
1 t
d(MDC-MDIO)
Delay time, MDC high to MDIO valid 0 390 ns
Figure 5-119. PRU-ICSS MDIO_DATA Timing – Output Mode
5.9.6.22.3.2 PRU-ICSS MII_RT Electrical Data and Timing
NOTE
In order to guarantee the MII_RT IO timing values published in the device data manual, the
ICSS_CLK clock must be configured for 200MHz (default value) and the TX_CLK_DELAY
bitfield in the PRUSS_MII_RT_TXCFG0/1 register must be set to 6h (non-default value).
Table 5-169. PRU-ICSS MII_RT Timing Requirements – MII[x]_RXCLK
NO. PARAMETER DESCRIPTION SPEED MIN MAX UNIT
1 t
c(RX_CLK)
Cycle time, RX_CLK 10 Mbps 399.96 400.04 ns
100 Mbps 39.996 40.004 ns
2 t
w(RX_CLKH)
Pulse duration, RX_CLK high 10 Mbps 140 260 ns
100 Mbps 14 26 ns
3 t
w(RX_CLKL)
Pulse duration, RX_CLK low 10 Mbps 140 260 ns
100 Mbps 14 26 ns
Figure 5-120. PRU-ICSS MII[x]_RXCLK Timing