MDIO_CLK (Output)
1
2
MDIO_DATA (Input)
SPRS91x_TIMING_PRU_MII_RT_01
EDC_LATCHx_IN
1
SPRS91x_TIMING_PRU_ECAT_04
295
AM5706, AM5708
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SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
(1) ICSS_IEP_CLK clock period
Figure 5-116. PRU-ICSS ECAT LATCHx_IN Timing
Table 5-165. PRU-ICSS ECAT Switching Requirements - Digital IOs
NO. PARAMETER DESCRIPTION MIN MAX UNIT
1 t
w(EDIO_OUTVALID)
Pulse duration, EDIO_OUTVALID 14 × P
(1)
32 × P
(1)
ns
2 t
d(EDIO_OUTVALID-
EDIO_DATA_OUT)
Delay time, EDIO_OUTVALID to EDIO_DATA_OUT 0.00 18 × P
(1)
ns
1 t
sk(EDIO_DATA_OUT)
EDIO_DATA_OUT skew 8 ns
(1) ICSS_IEP_CLK clock period
5.9.6.22.3 PRU-ICSS MII_RT and Switch
5.9.6.22.3.1 PRU-ICSS MDIO Electrical Data and Timing
Table 5-166. PRU-ICSS MDIO Timing Requirements – MDIO_DATA
NO. PARAMETER DESCRIPTION MIN MAX UNIT
1 t
su(MDIO-MDC)
Setup time, MDIO valid before MDC high 90 ns
2 t
h(MDIO-MDC)
Hold time, MDIO valid from MDC high 0 ns
Figure 5-117. PRU-ICSS MDIO_DATA Timing - Input Mode
Table 5-167. PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
NO. PARAMETER DESCRIPTION MIN MAX UNIT
1 t
c(MDC)
Cycle time, MDC 400 ns
2 t
w(MDCH)
Pulse duration, MDC high 160 ns
3 t
w(MDCL)
Pulse duration, MDC low 160 ns
4 t
t(MDC)
Transition time, MDC 5 ns