EDIO_LATCH_IN
3
1
2
EDIO_DATA_IN[7:0]
SPRS91x_TIMING_PRU_ECAT_01
ENDATx_IN
ENDATx_CLK
2
1
4
ENDATx_OUT
ENDATx_OUT_EN
SPRS91x_TIMING_PRU_09
3
293
AM5706, AM5708
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SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
Figure 5-112. PRU-ICSS PRU EnDAT Timing
5.9.6.22.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
5.9.6.22.2.1 PRU-ICSS ECAT Electrical Data and Timing
Table 5-161. PRU-ICSS ECAT Timing Requirements – Input Validated With LATCH_IN
NO. PARAMETER DESCRIPTION MIN MAX UNIT
1 t
w(EDIO_LATCH_IN)
Pulse width, EDIO_LATCH_IN 100.00 ns
2 t
su(EDIO_DATA_IN-
EDIO_LATCH_IN)
Setup time, EDIO_DATA_IN valid before EDIO_LATCH_IN active
edge
20.00 ns
3 t
h(EDIO_LATCH_IN-
EDIO_DATA_IN)
Hold time, EDIO_DATA_IN valid after EDIO_LATCH_IN active edge 20.00 ns
Figure 5-113. PRU-ICSS ECAT Input Validated with LATCH_IN Timing