SDx_CLK
SDx_D
1
2 3
SPRS91x_TIMING_PRU_08
SDx_CLK
SDx_D
1
2 3
SPRS91x_TIMING_PRU_07
292
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Specifications Copyright © 2016–2017, Texas Instruments Incorporated
5.9.6.22.1.4 PRU-ICSS PRU Sigma Delta and EnDAT Modes
Table 5-158. PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
NO. PARAMETER DESCRIPTION MIN MAX UNIT
1 tw(SDx_CLK) Pulse width, SDx_CLK 20 ns
2 tsu(SDx_D-SDx_CLK) Setup time, SDx_D valid before SDx_CLK active edge 10 ns
3 th(SDx_CLK-SDx_D) Hold time, SDx_D valid before SDx_CLK active edge 5 ns
Figure 5-110. PRU-ICSS PRU SD_CLK Falling Active Edge
Figure 5-111. PRU-ICSS PRU SD_CLK Rising Active Edge
Table 5-159. PRU-ICSS PRU Timing Requirements - EnDAT Mode
NO. PARAMETER DESCRIPTION MIN MAX UNIT
1 tw(ENDATx_IN) Pulse width, ENDATx_IN 40 ns
Table 5-160. PRU-ICSS PRU Switching Requirements - EnDAT Mode
NO. PARAMETER DESCRIPTION MIN MAX UNIT
2 tw(ENDATx_CLK) Pulse width, ENDATx_CLK 20 ns
3 td(ENDATx_OUT-
ENDATx_CLK)
Delay time, ENDATx_CLK fall to ENDATx_OUT -10 10 ns
4 td(ENDATx_OUT_EN-
ENDATx_CLK)
Delay time, ENDATx_CLK Fall to ENDATx_OUT_EN -10 10 ns