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AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Specifications Copyright © 2016–2017, Texas Instruments Incorporated
Table 5-152. Manual Functions Mapping for MMC3 (continued)
BALL BALL NAME MMC3_MANUAL1 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) 0
Y4 mmc3_dat0 362 0 CFG_MMC3_DAT0_OEN mmc3_dat0
Y4 mmc3_dat0 0 0 CFG_MMC3_DAT0_OUT mmc3_dat0
AA2 mmc3_dat1 7 0 CFG_MMC3_DAT1_IN mmc3_dat1
AA2 mmc3_dat1 333 0 CFG_MMC3_DAT1_OEN mmc3_dat1
AA2 mmc3_dat1 0 0 CFG_MMC3_DAT1_OUT mmc3_dat1
AA3 mmc3_dat2 0 0 CFG_MMC3_DAT2_IN mmc3_dat2
AA3 mmc3_dat2 402 0 CFG_MMC3_DAT2_OEN mmc3_dat2
AA3 mmc3_dat2 0 0 CFG_MMC3_DAT2_OUT mmc3_dat2
W2 mmc3_dat3 203 0 CFG_MMC3_DAT3_IN mmc3_dat3
W2 mmc3_dat3 549 0 CFG_MMC3_DAT3_OEN mmc3_dat3
W2 mmc3_dat3 1 0 CFG_MMC3_DAT3_OUT mmc3_dat3
Y3 mmc3_dat4 121 0 CFG_MMC3_DAT4_IN mmc3_dat4
Y3 mmc3_dat4 440 0 CFG_MMC3_DAT4_OEN mmc3_dat4
Y3 mmc3_dat4 206 0 CFG_MMC3_DAT4_OUT mmc3_dat4
AA1 mmc3_dat5 336 0 CFG_MMC3_DAT5_IN mmc3_dat5
AA1 mmc3_dat5 283 0 CFG_MMC3_DAT5_OEN mmc3_dat5
AA1 mmc3_dat5 174 0 CFG_MMC3_DAT5_OUT mmc3_dat5
AA4 mmc3_dat6 320 0 CFG_MMC3_DAT6_IN mmc3_dat6
AA4 mmc3_dat6 443 0 CFG_MMC3_DAT6_OEN mmc3_dat6
AA4 mmc3_dat6 0 0 CFG_MMC3_DAT6_OUT mmc3_dat6
AB1 mmc3_dat7 2 0 CFG_MMC3_DAT7_IN mmc3_dat7
AB1 mmc3_dat7 344 0 CFG_MMC3_DAT7_OEN mmc3_dat7
AB1 mmc3_dat7 0 0 CFG_MMC3_DAT7_OUT mmc3_dat7
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-31 and described in Device TRM, Control
Module Chapter.
5.9.6.21 GPIO
The general-purpose interface combines eight general-purpose input/output (GPIO) banks. Each GPIO
module provides up to 32 dedicated general-purpose pins with input and output capabilities; thus, the
general-purpose interface supports up to 186 pins.
These pins can be configured for the following applications:
• Data input (capture)/output (drive)
• Keyboard interface with a debounce cell
• Interrupt generation in active mode upon the detection of external events. Detected events are
processed by two parallel independent interrupt-generation submodules to support biprocessor
operations
• Wake-up request generation in idle mode upon the detection of external events
NOTE
For more information, see the General-Purpose Interface chapter of the Device TRM.
