SDR122
SDR121
SDR120
SDR126
SDR125
SDR128
SDR127
mmcj_clk
mmcj_cmd
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_11
284
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Specifications Copyright © 2016–2017, Texas Instruments Incorporated
Table 5-143. Switching Characteristics for MMC3 - SDR12 Mode
(2)
(continued)
NO. PARAMETER DESCRIPTION MIN MAX UNIT
SDR122 t
w(clkL)
Pulse duration, mmc3_clk low 0.5 × P-
0.270
(1)
ns
SDR123 t
d(clkL-cmdV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition -19.13 16.93 ns
SDR124 t
d(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition -19.13 16.93 ns
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
Table 5-144. Timing Requirements for MMC4 - SDR12 Mode
(1)
NO. PARAMETER DESCRIPTION MIN MAX UNIT
SDR125 t
su(cmdV-clkH)
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge 25.99 ns
SDR126 t
h(clkH-cmdV)
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge 1.6 ns
SDR127 t
su(dV-clkH)
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge 25.99 ns
SDR128 t
h(clkH-dV)
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge 1.6 ns
(1) j in [i:0] = 3
Table 5-145. Switching Characteristics for MMC4 - SDR12 Mode
(2)
NO. PARAMETER DESCRIPTION MIN MAX UNIT
SDR120 fop(clk) Operating frequency, mmc4_clk 24 MHz
SDR121 t
w(clkH)
Pulse duration, mmc4_clk high 0.5 × P-
0.270
(1)
ns
SDR122 t
w(clkL)
Pulse duration, mmc4_clk low 0.5 × P-
0.270
(1)
ns
SDR125 t
d(clkL-cmdV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition -19.13 16.93 ns
SDR126 t
d(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition -19.13 16.93 ns
(1) P = output mmc4_clk period in ns
(2) j in [i:0] = 3
Figure 5-98. MMC/SD/SDIOj in - SDR12 - Receiver Mode