mmcj_clk
mmcj_cmd
mmcj_dat[i:0]
HS1
HS2LHS2H
HS5
HS6
HS5
HS6
SPRS906_TIMING_MMC3_10
mmcj_clk
mmcj_cmd
mmcj_dat[i:0]
HS1
HS2L
HS2H
HS3
HS4
HS7
HS8
SPRS906_TIMING_MMC3_09
283
AM5706, AM5708
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SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
Table 5-141. Switching Characteristics for MMC4 - High Speed Mode
(2)
(continued)
NO. PARAMETER DESCRIPTION MIN MAX UNIT
HS2L t
w(clkL)
Pulse duration, mmc4_clk low 0.5 × P-
0.270
(1)
ns
HS5 t
d(clkL-cmdV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition -8.8 6.6 ns
HS6 t
d(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition -8.8 6.6 ns
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
Figure 5-96. MMC/SD/SDIOj in - High Speed 3.3V Signaling - Receiver Mode
Figure 5-97. MMC/SD/SDIOj in - High Speed 3.3V Signaling - Transmitter Mode
5.9.6.20.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
Figure 5-98, Figure 5-99, and Table 5-142, through Table 5-145 present Timing requirements and
Switching characteristics for MMC3 and MMC4 - SD and SDIO SDR12 in receiver and transmitter mode.
Table 5-142. Timing Requirements for MMC3 - SDR12 Mode
(1)
NO. PARAMETER DESCRIPTION MIN MAX UNIT
SDR125 t
su(cmdV-clkH)
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge 25.99 ns
SDR126 t
h(clkH-cmdV)
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge 1.6 ns
SDR127 t
su(dV-clkH)
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge 25.99 ns
SDR128 t
h(clkH-dV)
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge 1.6 ns
(1) i in [i:0] = 7
Table 5-143. Switching Characteristics for MMC3 - SDR12 Mode
(2)
NO. PARAMETER DESCRIPTION MIN MAX UNIT
SDR120 fop(clk) Operating frequency, mmc3_clk 24 MHz
SDR121 t
w(clkH)
Pulse duration, mmc3_clk high 0.5 × P-
0.270
(1)
ns