DS2
DS1
DS0
DS6
DS5
DS8
DS7
mmcj_clk
mmcj_cmd
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_07
281
AM5706, AM5708
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SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
Table 5-135. Switching Characteristics for MMC3 - SD/SDIO Default Speed Mode
(2)
(continued)
NO. PARAMETER DESCRIPTION MIN MAX UNIT
DS2 t
w(clkL)
Pulse duration, mmc3_clk low 0.5 × P-
0.270
(1)
ns
DS3 t
d(clkL-cmdV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition -14.93 14.93 ns
DS4 t
d(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition -14.93 14.93 ns
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
Table 5-136. Timing Requirements for MMC4 - Default Speed Mode
(1)
NO. PARAMETER DESCRIPTION MIN MAX UNIT
DS5 t
su(cmdV-clkH)
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge 5.11 ns
DS6 t
h(clkH-cmdV)
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge 20.46 ns
DS7 t
su(dV-clkH)
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge 5.11 ns
DS8 t
h(clkH-dV)
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge 20.46 ns
(1) i in [i:0] = 3
Table 5-137. Switching Characteristics for MMC4 - Default Speed Mode
(2)
NO. PARAMETER DESCRIPTION MIN MAX UNIT
DS0 fop(clk) Operating frequency, mmc4_clk 24 MHz
DS1 t
w(clkH)
Pulse duration, mmc4_clk high 0.5 × P-
0.270
(1)
ns
DS2 t
w(clkL)
Pulse duration, mmc4_clk low 0.5 × P-
0.270
(1)
ns
DS3 t
d(clkL-cmdV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition -14.93 14.93 ns
DS4 t
d(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition -14.93 14.93 ns
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
Figure 5-94. MMC/SD/SDIOj in - Default Speed - Receiver Mode