mmc _clk2
mmc _cmd2
mmc _dat2 [7:0]
DDR1
DDR2
DDR2
DDR5
DDR5
DDR6
DDR6
DDR6
DDR6
DDR5
DDR5
DDR6
DDR6
MMC2_08
mmc _clk2
mmc _cmd2
mmc _dat2 [7:0]
DDR1
DDR2H
DDR2L
DDR3 DDR4
DDR7
DDR8
DDR7
DDR8
DDR7
DDR8
DDR7
SPRS906_TIMING_MMC2_07
278
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Specifications Copyright © 2016–2017, Texas Instruments Incorporated
Table 5-131. Switching Characteristics for MMC2 - JC64 High Speed DDR Mode (continued)
NO. PARAMETER DESCRIPTION MIN MAX UNIT
DDR5 t
d(clk-cmdV)
Delay time, mmc2_clk transition to mmc2_cmd transition 2.9 7.14 ns
DDR6 t
d(clk-dV)
Delay time, mmc2_clk transition to mmc2_dat[7:0] transition 2.9 7.14 ns
(1) P = output mmc2_clk period in ns
Figure 5-92. MMC/SD/SDIO in - High Speed DDR JC64 - Receiver Mode
Figure 5-93. MMC/SD/SDIO in - High Speed DDR JC64 - Transmitter Mode
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-31 and described in Device TRM, Control
Module Chapter.
Virtual IO Timings Modes must be used to guaranteed some IO timings for MMC2. See Table 5-29 Modes
Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 5-132 Virtual
Functions Mapping for MMC2 for a definition of the Virtual modes.
Table 5-132 presents the values for DELAYMODE bitfield.
Table 5-132. Virtual Functions Mapping for MMC2
BALL BALL NAME Delay Mode Value MUXMODE
MMC2_VIRTUAL2 1
A6 gpmc_cs1 13 mmc2_cmd
A4 gpmc_a19 13 mmc2_dat4