mmc _clk2
mmc _cmd2
mmc _dat2 [7:0]
JC645 JC645
JC646 JC646
JC641
JC642HJC642L
MMC2_04
mmc _clk2
mmc _cmd2
mmc _dat2 [7:0]
JC644
JC648
JC643
JC647
JC641
JC642HJC642L
SPRS906_TIMING_MMC2_03
276
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Specifications Copyright © 2016–2017, Texas Instruments Incorporated
Table 5-128. Switching Characteristics for MMC2 - JC64 High Speed SDR Mode
NO. PARAMETER DESCRIPTION MIN MAX UNIT
JC641 fop(clk) Operating frequency, mmc2_clk 48 MHz
JC642H t
w(clkH)
Pulse duration, mmc2_clk high 0.5 × P-
0.172
(1)
ns
JC642L t
w(clkL)
Pulse duration, mmc2_clk low 0.5 × P-
0.172
(1)
ns
JC645 t
d(clkL-cmdV)
Delay time, mmc2_clk falling clock edge to mmc2_cmd transition -6.64 6.64 ns
JC646 t
d(clkL-dV)
Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition -6.64 6.64 ns
(1) P = output mmc2_clk period in ns
Figure 5-89. MMC/SD/SDIO in - High Speed JC64 - Receiver Mode
Figure 5-90. MMC/SD/SDIO in - High Speed JC64 - transmitter Mode
5.9.6.20.2.3 High-speed HS200 JEDS84 SDR, 8-bit data, half cycle
Table 5-129 presents Switching characteristics for MMC2 - HS200 in transmitter mode (see Figure 5-91).