SSDR2
mmc2_clk
mmc2_cmd
mmc2_dat[7:0]
SSDR1
SSDR2
SSDR3
SSDR4
SPRS906_TIMING_MMC2_02
mmc2_clk
mmc2_cmd
mmc2_dat[7:0]
SSDR2
SSDR2
SSDR1
SSDR6
SSDR5
SSDR8
SSDR7
SPRS906_TIMING_MMC2_01
275
AM5706, AM5708
www.ti.com
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
Submit Documentation Feedback
Product Folder Links: AM5706 AM5708
SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
Table 5-126. Switching Characteristics for MMC2 - JC64 Standard SDR Mode
NO. PARAMETER DESCRIPTION MIN MAX UNIT
SSDR1 fop(clk) Operating frequency, mmc2_clk 24 MHz
SSDR2H t
w(clkH)
Pulse duration, mmc2_clk high 0.5 × P-
0.172
(1)
ns
SSDR2L t
w(clkL)
Pulse duration, mmc2_clk low 0.5 × P-
0.172
(1)
ns
SSDR3 t
d(clkL-cmdV)
Delay time, mmc2_clk falling clock edge to mmc2_cmd transition -16.96 16.96 ns
SSDR4 t
d(clkL-dV)
Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition -16.96 16.96 ns
(1) P = output mmc2_clk period in ns
Figure 5-87. MMC/SD/SDIO in - Standard JC64 - Receiver Mode
Figure 5-88. MMC/SD/SDIO in - Standard JC64 - Transmitter Mode
5.9.6.20.2.2 High-speed JC64 SDR, 8-bit data, half cycle
Table 5-127 and Table 5-128 present Timing requirements and Switching characteristics for MMC2 - High
speed SDR in receiver and transmitter mode (see Figure 5-89 and Figure 5-90).
Table 5-127. Timing Requirements for MMC2 - JC64 High Speed SDR Mode
NO. PARAMETER DESCRIPTION MIN MAX UNIT
JC643 t
su(cmdV-clkH)
Setup time, mmc2_cmd valid before mmc2_clk rising clock edge 5.6 ns
JC644 t
h(clkH-cmdV)
Hold time, mmc2_cmd valid after mmc2_clk rising clock edge 2.6 ns
JC647 t
su(dV-clkH)
Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge 5.6 ns
JC648 t
h(clkH-dV)
Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge 2.6 ns