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SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
Table 5-124. Manual Functions Mapping for MMC1
BALL BALL NAME MMC1_MANUAL1 MMC1_MANUAL2 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 0
U3 mmc1_clk 588 0 - - CFG_MMC1_CLK_IN mmc1_clk
V4 mmc1_cmd 1000 0 - - CFG_MMC1_CMD_IN mmc1_cmd
V3 mmc1_dat0 1375 0 - - CFG_MMC1_DAT0_IN mmc1_dat0
V2 mmc1_dat1 1000 0 - - CFG_MMC1_DAT1_IN mmc1_dat1
W1 mmc1_dat2 1000 0 - - CFG_MMC1_DAT2_IN mmc1_dat2
V1 mmc1_dat3 1000 0 - - CFG_MMC1_DAT3_IN mmc1_dat3
U3 mmc1_clk 1230 0 520 320 CFG_MMC1_CLK_OUT mmc1_clk
V4 mmc1_cmd 0 0 0 0 CFG_MMC1_CMD_OUT mmc1_cmd
V3 mmc1_dat0 56 0 40 0 CFG_MMC1_DAT0_OUT mmc1_dat0
V2 mmc1_dat1 76 0 83 0 CFG_MMC1_DAT1_OUT mmc1_dat1
W1 mmc1_dat2 91 0 98 0 CFG_MMC1_DAT2_OUT mmc1_dat2
V1 mmc1_dat3 99 0 106 0 CFG_MMC1_DAT3_OUT mmc1_dat3
V4 mmc1_cmd 0 0 51 0 CFG_MMC1_CMD_OEN mmc1_cmd
V3 mmc1_dat0 0 0 0 0 CFG_MMC1_DAT0_OEN mmc1_dat0
V2 mmc1_dat1 0 0 363 0 CFG_MMC1_DAT1_OEN mmc1_dat1
W1 mmc1_dat2 0 0 199 0 CFG_MMC1_DAT2_OEN mmc1_dat2
V1 mmc1_dat3 0 0 273 0 CFG_MMC1_DAT3_OEN mmc1_dat3
5.9.6.20.2 MMC2 — eMMC
MMC2 interface is compliant with the JC64 eMMC Standard v4.5 and it supports the following eMMC applications:
• Standard JC64 SDR, 8-bit data, half cycle
• High-speed JC64 SDR, 8-bit data, half cycle
• High-speed HS200 JEDS84, 8-bit data, half cycle
• High-speed JC64 DDR, 8-bit data
NOTE
For more information, see the eMMC/SD/SDIO chapter of the Device TRM.