mmc _clk1
mmc _cmd1
mmc _dat[3:0]1
DDR500
DDR501 DDR502
DDR503(max) DDR503(min)
DDR504(max)
DDR504(min) DDR504(min)
DDR504(max)
MMC1_14
272
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Product Folder Links: AM5706 AM5708
Specifications Copyright © 2016–2017, Texas Instruments Incorporated
Figure 5-86. SDMMC - High Speed SD - DDR - Data/Command Transmit
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-31 and described in Device TRM, Control
Module Chapter.
Virtual IO Timings Modes must be used to guaranteed some IO timings for MMC1. See Table 5-29 Modes
Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 5-123 Virtual
Functions Mapping for MMC1 for a definition of the Virtual modes.
Table 5-123 presents the values for DELAYMODE bitfield.
Table 5-123. Virtual Functions Mapping for MMC1
BALL BALL NAME Delay Mode Value MUXMODE
MMC1_
VIRTUAL1
MMC1_
VIRTUAL4
MMC1_
VIRTUAL5
MMC1_
VIRTUAL6
0
U3 mmc1_clk 15 12 11 10 mmc1_clk
V4 mmc1_cmd 15 12 11 10 mmc1_cmd
V3 mmc1_dat0 15 12 11 10 mmc1_dat0
V2 mmc1_dat1 15 12 11 10 mmc1_dat1
W1 mmc1_dat2 15 12 11 10 mmc1_dat2
V1 mmc1_dat3 15 12 11 10 mmc1_dat3
NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for MMC1. See Table 5-29
Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-124
Manual Functions Mapping for MMC1 for a definition of the Manual modes.
Table 5-124 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in
the CFG_x registers.
