mmc1_clk
mmc1_cmd
mmc1_dat[3:0]
HSSD1
HSSD2LHSSD2H
HSSD5
HSSD6
HSSD5
HSSD6
SPRS906_TIMING_MMC1_04
mmc1_clk
mmc1_cmd
mmc1_dat[3:0]
HSSD1
HSSD2L
HSSD2H
HSSD3
HSSD4
HSSD7
HSSD8
SPRS906_TIMING_MMC1_03
267
AM5706, AM5708
www.ti.com
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Product Folder Links: AM5706 AM5708
SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
(1) P = output mmc1_clk period in ns
Figure 5-75. MMC/SD/SDIO in - High Speed - Receiver Mode
Figure 5-76. MMC/SD/SDIO in - High Speed - Transmitter Mode
5.9.6.20.1.3 SDR12, 4-bit data, half-cycle
Table 5-114 and Table 5-115 present Timing requirements and Switching characteristics for MMC1 -
SDR12 in receiver and transmitter mode (see Figure 5-77 and Figure 5-78).
Table 5-114. Timing Requirements for MMC1 - SD Card SDR12 Mode
NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
SDR12
5
t
su(cmdV-clkH)
Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
25.99 ns
SDR12
6
t
h(clkH-cmdV)
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
Pad Loopback Clock 1.6 ns
Internal Loopback Clock 1.6 ns
SDR12
7
t
su(dV-clkH)
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
25.99 ns
SDR12
8
t
h(clkH-dV)
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
Pad Loopback Clock 1.6 ns
Internal Loopback Clock 1.6 ns
Table 5-115. Switching Characteristics for MMC1 - SD Card SDR12 Mode
NO. PARAMETER DESCRIPTION MIN MAX UNIT
SDR120 fop(clk) Operating frequency, mmc1_clk 24 MHz
SDR121 t
w(clkH)
Pulse duration, mmc1_clk high 0.5 × P-
0.185
(1)
ns
SDR122 t
w(clkL)
Pulse duration, mmc1_clk low 0.5 × P-
0.185
(1)
ns
SDR123 t
d(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition -19.13 16.93 ns
SDR124 t
d(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition -19.13 16.93 ns