265
AM5706, AM5708
www.ti.com
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
Submit Documentation Feedback
Product Folder Links: AM5706 AM5708
SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
5.9.6.20 eMMC/SD/SDIO
The Device includes the following external memory interfaces 4 MultiMedia Card/Secure Digital/Secure
Digital Input Output Interface (MMC/SD/SDIO)
NOTE
The eMMC/SD/SDIOi (i = 1 to 4) controller is also referred to as MMCi.
5.9.6.20.1 MMC1—SD Card Interface
MMC1 interface is compliant with the SD Standard v3.01 and it supports the following SD Card
applications:
• Default speed, 4-bit data, SDR, half-cycle
• High speed, 4-bit data, SDR, half-cycle
• SDR12, 4-bit data, half-cycle
• SDR25, 4-bit data, half-cycle
• UHS-I SDR50, 4-bit data, half-cycle
• UHS-I SDR104, 4-bit data, half-cycle
• UHS-I DDR50, 4-bit data
NOTE
For more information, see the eMMC/SD/SDIO chapter of the Device TRM.
5.9.6.20.1.1 Default speed, 4-bit data, SDR, half-cycle
Table 5-110 and Table 5-111 present Timing requirements and Switching characteristics for MMC1 -
Default Speed in receiver and transmitter mode (see Figure 5-73 and Figure 5-74).
Table 5-110. Timing Requirements for MMC1 - SD Card Default Speed Mode
NO. PARAMETER DESCRIPTION MIN MAX UNIT
DSSD5 t
su(cmdV-clkH)
Setup time, mmc1_cmd valid before mmc1_clk rising clock edge 5.11 ns
DSSD6 t
h(clkH-cmdV)
Hold time, mmc1_cmd valid after mmc1_clk rising clock edge 20.46 ns
DSSD7 t
su(dV-clkH)
Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge 5.11 ns
DSSD8 t
h(clkH-dV)
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge 20.46 ns
Table 5-111. Switching Characteristics for MMC1 - SD Card Default Speed Mode
NO. PARAMETER DESCRIPTION MIN MAX UNIT
DSSD0 fop(clk) Operating frequency, mmc1_clk 24 MHz
DSSD1 t
w(clkH)
Pulse duration, mmc1_clk high 0.5 × P-
0.185
(1)
ns
DSSD2 t
w(clkL)
Pulse duration, mmc1_clk low 0.5 × P-
0.185
(1)
ns
DSSD3 t
d(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition -14.93 14.93 ns
DSSD4 t
d(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition -14.93 14.93 ns