1
mii _txclkn (input)
miin_txd3
miin_txen
− ,
(outputs)
miin_txd0
SPRS906_TIMING_GMAC_MIITX_04
mii _rxclkn (Input)
1
2
mii _rxd3n
mii _rxdv miin_rxer
−
, (Inputs)
mii _rxd0,n
n
SPRS906_TIMING_GMAC_MIIRCV_03
254
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Specifications Copyright © 2016–2017, Texas Instruments Incorporated
Table 5-90. Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s (continued)
NO. PARAMETER DESCRIPTION MIN MAX UNIT
2
t
h(RX_CLK-RXD)
Hold time, receive selected signals valid after miin_rxclk 8 nst
h(RX_CLK-RX_DV)
t
h(RX_CLK-RX_ER)
Figure 5-66. GMAC Receive Interface Timing MIIn operation
Table 5-91 and Figure 5-67 present timing requirements for GMAC MIIn Transmit 10/100Mbit/s.
Table 5-91. Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit
10/100 Mbits/s
NO. PARAMETER DESCRIPTION MIN MAX UNIT
1
t
d(TX_CLK-TXD)
Delay time, miin_txclk to transmit selected signals valid 0 25 ns
t
d(TX_CLK-TX_EN)
Figure 5-67. GMAC Transmit Interface Timing MIIn operation
In Table 5-92 are presented the specific groupings of signals (IOSET) for use with GMAC MII signals.
Table 5-92. GMAC MII IOSETs
SIGNALS IOSET5 IOSET6
BALL MUX BALL MUX
GMAC MII1
mii1_txd3 E11 8
mii1_txd2 A13 8
mii1_txd1 A12 8
mii1_txd0 B12 8
mii1_rxd3 B10 8
mii1_rxd2 A10 8
mii1_rxd1 F10 8
mii1_rxd0 E10 8
mii1_col E13 8
mii1_rxer B13 8
mii1_txer F11 8