cs
sclk
d[0]
d[3:1]
Bit n-1 Bit n-2
Bit 1
Bit 0
PHA=0
POL=0
Command
Command
Write Data
Write Data
Q4
Q7
Q2
Q3
Q1
Q6
Q6
Q5
SPRS85v_TIMING_OSPI1_04
Q8
Q9
Q6
cs
sclk
d[0]
d[3:1]
Bit n-1 Bit n-2
Bit 1
Bit 0
PHA=1
POL=1
Command
Command
Write Data
Write Data
Q4
Q7
Q6
Q3
Q2
Q1
Q6
Q6
Q5
SPRS85v_TIMING_OSPI1_03
Q8
Q6
229
AM5706, AM5708
www.ti.com
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Product Folder Links: AM5706 AM5708
SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
(1) P = SCLK period.
(2) Clock Modes 1 and 2 are not supported.
(3) The Device captures data on the falling clock edge in Clock Mode 0 and 3, as opposed to the traditional rising clock edge. Although
non-standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that
launch data on the falling edge in Clock Modes 0 and 3.
Figure 5-51. QSPI Write (Clock Mode 3)
Figure 5-52. QSPI Write (Clock Mode 0)
CAUTION
The I/O Timings provided in this section are valid only for some QSPI usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.