cs
sclk
d[0]
d[3:1]
Bit n-1 Bit n-2
Bit 1
Bit 0
PHA=1
POL=1
Command
Command
Read Data
Read Data
Bit 1
Bit 0
Read Data
Read Data
Q4
Q7
Q6
Q3
Q2
Q1
Q6
Q5
SPRS85v_TIMING_OSPI1_01
Q12
Q13
Q14
Q15
Q12
Q13
Q15
Q14
227
AM5706, AM5708
www.ti.com
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
Table 5-66. Switching Characteristics for QSPI (continued)
NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
Q2 t
w(SCLKL)
Pulse duration, sclk low Y × P-1
(1)
ns
Q3 t
w(SCLKH)
Pulse duration, sclk high Y × P-1
(1)
ns
Q4 t
d(CS-SCLK)
Delay time, sclk falling edge to cs active edge, CS3:0 Default Timing Mode -M × P-
1.6
(2)
(3)
-M ×
P+2.6
(2) (3)
ns
Q5 t
d(SCLK-CS)
Delay time, sclk falling edge to cs inactive edge,
CS3:0
Default Timing Mode N × P-
1.6
(2)
(3)
N ×
P+2.6
(2) (3)
ns
Q6 t
d(SCLK-D0)
Delay time, sclk falling edge to d[0] transition Default Timing Mode -1.6 2.6 ns
Q7 t
ena(CS-D0LZ)
Enable time, cs active edge to d[0] driven (lo-z) -P-3.5 -P+2.5 ns
Q8 t
dis(CS-D0Z)
Disable time, cs active edge to d[0] tri-stated (hi-z) -P-2.5 -P+2.0 ns
Q9 t
d(SCLK-D0)
Delay time, sclk first falling edge to first d[0] transition PHA=0 Only, Default
Timing Mode
-1.6-
P
(2)
2.6-P
(2)
ns
(1) The Y parameter is defined as follows:
If DCLK_DIV is 0 or ODD then, Y equals 0.5.
If DCLK_DIV is EVEN then, Y equals (DCLK_DIV/2) / (DCLK_DIV+1).
For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle distortion. The HSDIVIDER on
CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All required details about clock division
factor DCLK_DIV can be found in the device-specific Technical Reference Manual.
(2) P = SCLK period.
(3) M=QSPI_SPI_DC_REG.DDx + 1 when Clock Mode 0.
M=QSPI_SPI_DC_REG.DDx when Clock Mode 3.
N = 2 when Clock Mode 0.
N = 3 when Clock Mode 3.
Figure 5-49. QSPI Read (Clock Mode 3)