spim_cs(IN)
spi _sclkm (IN)
spi _sclkm (IN)
spi _m d(OUT)
spim_cs(IN)
spi _sclkm (IN)
spi _sclkm (IN)
spi _m d(OUT)
Bit n-1 Bit n-2 Bit n-3 Bit n-4
Bit 0
Bit n-1 Bit n-2 Bit n-3 Bit 1
Bit 0
PHA=0
EPOL=1
POL=0
POL=1
POL=0
POL=1
PHA=1
EPOL=1
SS6
SS3
SS1
SS3
SS1
SS3
SS1
SS2
SS1
SS6
SS6
SS8 SS9
SS7
SS8
SS2
SS3
SS2
SS2
SS6 SS6SS6
SS9
SPRS906_TIMING_McSPI_03
224
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Specifications Copyright © 2016–2017, Texas Instruments Incorporated
Table 5-64. Timing Requirements for SPI - Slave Mode (continued)
NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
SS7
(5)
t
d(CS-SOMI)
Delay time, spi_cs[x] active edge to mcspi_somi transition 20.95 ns
SS8
(1)
t
su(CS-SPICLK)
Setup time, spi_cs[x] valid before spi_sclk first edge 5 ns
SS9
(1)
t
h(SPICLK-CS)
Hold time, spi_cs[x] valid after spi_sclk last edge SPI1/2 5 ns
SPI3 7.5 ns
SPI4 6 ns
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) When operating the SPI interface in RX-only mode, the minimum Cycle time is 26ns (38.4MHz)
(3) 62.5ns Cycle time = 16 MHz
(4) P = SPICLK period.
(5) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
Figure 5-47. McSPI - Slave Mode Transmit