spim_cs(OUT)
spi _sclkm (OUT)
spi _sclkm (OUT)
spi _m d(IN)
spim_cs(OUT)
spi _sclkm (OUT)
spi _sclkm (OUT)
spi _m d(IN)
Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0
Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0
PHA=0
EPOL=1
PHA=1
EPOL=1
POL=0
POL=1
POL=0
POL=1
SM8 SM9
SM3
SM1
SM2
SM1
SM8 SM9SM3
SM1
SM2
SM1
SM2
SM3
SM2
SM3
SM4
SM5
SM4
SM5
SM4
SM4
SM5
SM5
SPRS906_TIMING_McSPI_02
223
AM5706, AM5708
www.ti.com
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
Figure 5-46. McSPI - Master Mode Receive
Table 5-64, Figure 5-47 and Figure 5-48 present Timing Requirements for McSPI - Slave Mode.
Table 5-64. Timing Requirements for SPI - Slave Mode
NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
SS1
(1)
t
c(SPICLK)
Cycle time, spi_sclk 62.5
(2)
(3)
ns
SS2
(1)
t
w(SPICLKL)
Typical Pulse duration, spi_sclk low 0.45 × P
(4)
ns
SS3
(1)
t
w(SPICLKH)
Typical Pulse duration, spi_sclk high 0.45 × P
(4)
ns
SS4
(1)
t
su(SIMO-SPICLK)
Setup time, spi_d[x] valid before spi_sclk active edge 5 ns
SS5
(1)
t
h(SPICLK-SIMO)
Hold time, spi_d[x] valid after spi_sclk active edge 5 ns
SS6
(1)
t
d(SPICLK-SOMI)
Delay time, spi_sclk active edge to mcspi_somi transition SPI1/2/3 2 26.6 ns
SPI4 2 20.1 ns