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AM5706, AM5708
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SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
CAUTION
The I/O timings provided in this section are applicable for all combinations of
signals for SPI1 and SPI2. However, the timings are valid only for SPI3 and
SPI4 if signals within a single IOSET are used. The IOSETS are defined in
Table 5-65.
Table 5-63, Figure 5-45 and Figure 5-46 present Timing Requirements for McSPI - Master Mode.
Table 5-63. Timing Requirements for SPI - Master Mode
(1)
NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
SM1 t
c(SPICLK)
Cycle time, spi_sclk
(1) (2)
SPI1/2/3/
4
20.8
(3)
ns
SM2 t
w(SPICLKL)
Typical Pulse duration, spi_sclk low
(1)
0.5 × P-1
(4)
ns
SM3 t
w(SPICLKH)
Typical Pulse duration, spi_sclk high
(1)
0.5 × P-1
(4)
ns
SM4 t
su(MISO-SPICLK)
Setup time, spi_d[x] valid before spi_sclk active edge
(1)
3.5 ns
SM5 t
h(SPICLK-MISO)
Hold time, spi_d[x] valid after spi_sclk active edge
(1)
3.7 ns
SM6 t
d(SPICLK-SIMO)
Delay time, spi_sclk active edge to spi_d[x] transition
(1)
SPI1 -3.57 4.1 ns
SPI2 -3.9 3.6 ns
SPI3 -4.9 4.7 ns
SPI4 -4.3 4.5 ns
SM7 t
d(CS-SIMO)
Delay time, spi_cs[x] active edge to spi_d[x] transition 5 ns
SM8 t
d(CS-SPICLK)
Delay time, spi_cs[x] active to spi_sclk first edge
(1)
MASTER
_PHA0
(5)
B-4.2
(6)
ns
MASTER
_PHA1
(5)
A-4.2
(7)
ns
SM9 t
d(SPICLK-CS)
Delay time, spi_sclk last edge to spi_cs[x] inactive
(1)
MASTER
_PHA0
(5)
A-4.2
(7)
ns
MASTER
_PHA1
(5)
B-4.2
(6)
ns
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) Related to the SPI_CLK maximum frequency.
(3) 20.8ns cycle time = 48MHz
(4) P = SPICLK period.
(5) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
(6) B = (TCS + 0.5) × TSPICLKREF × Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even ≥2.
(7) When P = 20.8 ns, A = (TCS + 1) × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS
+ 0.5) × Fratio × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.