2
1
Start
Bit
Data Bits
UART_TXD
3
Data Bits
Bit
Start
4
UART_RXD
SPRS961_TIMING_UART_01
220
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Specifications Copyright © 2016–2017, Texas Instruments Incorporated
Table 5-62. Switching Characteristics Over Recommended Operating Conditions for UART (continued)
NO. PARAMETER DESCRIPTION MIN MAX UNIT
3 t
w(RTS)
Pulse width, transmit start bit, 15/30/100 pF high or low U - 2
(1)
U + 2
(1)
ns
(1) U = UART baud time = 1/programmed baud rate
Figure 5-44. UART Timing
In are presented the specific groupings of signals (IOSET) for use with UART.
5.9.6.13 McSPI
The McSPI is a master/slave synchronous serial bus. There are four separate McSPI modules (SPI1,
SPI2, SPI3, and SPI4) in the device. All these four modules support up to four external devices (four chip
selects) and are able to work as both master and slave.
The McSPI modules include the following main features:
• Serial clock with programmable frequency, polarity, and phase for each channel
• Wide selection of SPI word lengths, ranging from 4 to 32 bits
• Up to four master channels, or single channel in slave mode
• Master multichannel mode:
– Full duplex/half duplex
– Transmit-only/receive-only/transmit-and-receive modes
– Flexible input/output (I/O) port controls per channel
– Programmable clock granularity
– SPI configuration per channel. This means, clock definition, polarity enabling and word width
• Power management through wake-up capabilities
• Programmable timing control between chip select and external clock generation
• Built-in FIFO available for a single channel.
• Each SPI module supports multiple chip select pins spim_cs[i], where i = 1 to 4.
NOTE
For more information, see the Serial Communication Interface section of the device TRM.
NOTE
The McSPIm module (m = 1 to 4) is also referred to as SPIm.
