1-WIRE
t
LOWR
t
RDV
and__ t
REL
t
SLOT
_ _and t
REC
SPRS906_TIMING_HDQ1W_06
1-WIRE
t
RSTH
t
PDL
t
PDH
t
RTSL
SPRS906_TIMING_HDQ1W_05
HDQ
Break
0_(LSB)
1 6 7_(MSB)
t
RSPS
1
6
Command_byte_written Data_byte_received
0_(LSB)
SPRS906_TIMING_HDQ1W_04
218
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Specifications Copyright © 2016–2017, Texas Instruments Incorporated
Figure 5-40. HDQ Communication Timing
5.9.6.11.2 HDQ/1-Wire—1-Wire Mode
Table 5-59 and Table 5-60 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-41, Figure 5-42 and Figure 5-43).
Table 5-59. HDQ / 1-Wire Timing Requirements - 1-Wire Mode
NO. PARAMETER DESCRIPTION MIN MAX UNIT
10 t
PDH
Presence pulse delay high 15 60 µs
11 t
PDL
Presence pulse delay low 60 240 µs
12 t
RDV
Read data valid time t
LOWR
15 µs
13 t
REL
Read data release time 0 45 µs
Table 5-60. HDQ / 1-Wire Switching Characteristics - 1-Wire Mode
NO. PARAMETER DESCRIPTION MIN MAX UNIT
14 t
RSTL
Reset time low 480 960 µs
15 t
RSTH
Reset time high 480 µs
16 t
SLOT
Bit cycle time 60 120 µs
17 t
LOW1
Write bit-one time 1 15 µs
18 t
LOW0
Write bit-zero time
(2)
60 120 µs
19 t
REC
Recovery time 1 µs
20 t
LOWR
Read bit strobe time
(1)
1 15 µs
(1) t
LOWR
(low pulse sent by the master) must be short as possible to maximize the master sampling window.
(2) t
LOWR
must be less than t
SLOT
.
Figure 5-41. 1-Wire—Break (Reset)
Figure 5-42. 1-Wire—Read Bit (Data)
