10
8
4
3
7
12
5
6
14
2
3
13
Stop Start Repeated
Start
Stop
I2Ci_SDA
I2Ci_SCL
1
11
9
SPRS906_TIMING_I2C_01
215
AM5706, AM5708
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SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
Table 5-55. Timing Requirements for I
2
C HS-Mode (I
2
C3/4/5 Only)
(1)
(continued)
NO. PARAMETER DESCRIPTION C
b
= 100 pF MAX C
b
= 400 pF
(2)
UNIT
MIN MAX MIN MAX
4 t
w(SCLL)
LOW period of the SCLH clock 160 320 ns
5 t
w(SCLH)
HIGH period of the SCLH clock 60 120 ns
6 t
su(SDAV-SCLH)
Setup time, SDA valid vefore
SCL high
10 10 ns
7 t
h(SCLL-SDAV)
Hold time, SDA valid after SCL
low
0
(3)
70 0
(3)
150 ns
13 t
su(SCLH-SDAH)
Setup time, SCL high before
SDA high (for a STOP condition)
160 160 ns
14 t
w(SP)
Pulse duration, spike (must be
suppressed)
0 10 0 10 ns
15 C
b
(2)
Capacitive load for SDAH and
SCLH lines
100 400 pF
16 C
b
Capacitive load for SDAH + SDA
line and SCLH + SCL line
400 400 pF
(1) I
2
C HS-Mode is only supported on I
2
C3/4/5. I2C HS-Mode is not supported on I
2
C1/2.
(2) For bus line loads C
b
between 100 and 400 pF the timing parameters must be linearly interpolated.
(3) A device must internally provide a Data hold time to bridge the undefined part between V
IH
and V
IL
of the falling edge of the SCLH
signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
Figure 5-35. I2C Receive Timing
Table 5-56 and Figure 5-36 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
Table 5-56. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
(2)
NO. PARAMETER DESCRIPTION
STANDARD MODE FAST MODE
UNIT
MIN MAX MIN MAX
16 t
c(SCL)
Cycle time, SCL 10 2.5 µs
17 t
su(SCLH-SDAL)
Setup time, SCL high before SDA low (for a
repeated START condition)
4.7 0.6 µs
18 t
h(SDAL-SCLL)
Hold time, SCL low after SDA low (for a
START and a repeated START condition)
4 0.6 µs
19 t
w(SCLL)
Pulse duration, SCL low 4.7 1.3 µs
20 t
w(SCLH)
Pulse duration, SCL high 4 0.6 µs
21 t
su(SDAV-SCLH)
Setup time, SDA valid before SCL high 250 100 ns