GPMC_FCLK
gpmc_csi
gpmc_ben0
gpmc_ _aleadvn
gpmc_oen_ren
gpmc_wen
gpmc_ad[15:0]
DATA
GNF0
GNF1
GNF4
GNF6
GNF9
GNF3
GPMC_16
GPMC_FCLK
gpmc_csi
gpmc_ben0
gpmc_ _aleadvn
gpmc_oen_ren
gpmc_ad[15:0]
gpmc_waitj
DATA
GNF10
GNF13
GNF14
GNF15
GNF12
GPMC_15
209
AM5706, AM5708
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SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
Figure 5-33. GPMC / NAND Flash - Data Read Cycle Timing
(1)(2)(3)
(1) GNF12 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional
clock edge. GNF12 value must be stored inside AccessTime register bits field.
(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(3) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.
Figure 5-34. GPMC / NAND Flash - Data Write Cycle Timing
(1)
(1) In gpmc_csi, i = 0 to 7.
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-31 and described in Device TRM, Control
Module Chapter.
