gpmc_fclk
gpmc_clk
gpmc_csi
gpmc_ben0
gpmc_ 1ben
gpmc_ _aleadvn
gpmc_wen
gpmc_ad[15:0]
gpmc_waitj
DIR
Address (MSB)
Valid Address (LSB) Data OUT
OUT
FA0
FA1
FA9
FA10
FA3
FA25
FA29
FA12
FA27
FA28
FA0
FA10
GPMC_12
gpmc_a27
gpmc_a[10:1]
206
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Specifications Copyright © 2016–2017, Texas Instruments Incorporated
Figure 5-30. GPMC / Multiplexed NOR Flash - Asynchronous Write - Single Word Timing
(1)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
5.9.6.8.3 GPMC/NAND Flash Interface Asynchronous Timing
CAUTION
The I/O Timings provided in this section are valid only for some GPMC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
Table 5-51 and Table 5-52 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see Figure 5-31, Figure 5-32, Figure 5-33 and Figure 5-34).
Table 5-51. GPMC/NAND Flash Interface Timing Requirements
NO. PARAMETER DESCRIPTION MIN MAX UNIT
GNF12 t
acc(DAT)
Data maximum access time (GPMC_FCLK Cycles) J
(1)
cycles
- t
su(DV-OEH)
Setup time, read gpmc_ad[15:0] valid before
gpmc_oen_ren high
1.9 ns
- t
h(OEH-DV)
Hold time, read gpmc_ad[15:0] valid after
gpmc_oen_ren high
1 ns