gpmc_fclk
gpmc_clk
gpmc_csi
gpmc_a[ :1]27
gpmc_ben0
gpmc_be 1n
gpmc_ _aleadvn
gpmc_wen
gpmc_ d[15:0]a
gpmc_waitj
DIR
Valid Address
Data OUT
OUT
FA0
FA1
FA10
FA3
FA25
FA29
FA9
FA12
FA27
FA0
FA10
GPMC_10
204
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Specifications Copyright © 2016–2017, Texas Instruments Incorporated
Figure 5-28. GPMC / NOR Flash - Asynchronous Write - Single Word Timing
(1)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.