vouti_clk
vouti_vsync
vouti_hsync
vouti_d[23:0]
vouti_de
vouti_fld
data_1 data_2 data_n
odd
even
D1
D2
D3
D6
D6
D5
D6
D6
SWPS049-018
D4
vouti_clk
Falling-edge Clock Reference
Rising-edge Clock Reference
183
AM5706, AM5708
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SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
Figure 5-18. DPI Video Output
(1)(2)(3)
(1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
(2) The polarity and the pulse width of vouti_hsync and vouti_vsync are programmable, refer to the DSS section of the device TRM.
(3) The vouti_clk frequency can be configured, refer to the DSS section of the device TRM.
In Table 5-41 are presented the specific groupings of signals (IOSET) for use with VOUT2.
Table 5-41. VOUT2 IOSETs
SIGNALS IOSET1
BALL MUX
vout2_d23 C8 4
vout2_d22 B9 4
vout2_d21 A7 4
vout2_d20 A9 4
vout2_d19 A8 4
vout2_d18 A11 4
vout2_d17 F10 4
vout2_d16 A10 4
vout2_d15 B10 4
vout2_d14 E10 4
vout2_d13 D10 4
vout2_d12 C10 4
vout2_d11 B11 4
vout2_d10 D11 4