vinx_clki
(positive-edge clocking)
V4
vinx_d[23:0]/sig
V5
vinx_clki
(negative-edge clocking)
SPRS8xx_VIP_02
vinx_clki
V2
V1
V3
SPRS906_TIMING_VIP_01
169
AM5706, AM5708
www.ti.com
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
Submit Documentation Feedback
Product Folder Links: AM5706 AM5708
SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
Table 5-30. Timing Requirements for VIP
(3)(4)(5)
(continued)
NO. PARAMETER DESCRIPTION MIN MAX UNIT
V6 t
h(CLK-CTL/DATA)
Input hold time, Control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci)
and Data (vinx_dn) valid from vinx_clki transition
(3) (4) (5)
-0.05
(2)
ns
(1) For maximum frequency of 165 MHz.
(2) P = vinx_clki period.
(3) x in vinx = 1a, 1b, 2a, 2b.
(4) n in dn = 0 to 7 when x = 1b, 2b.
n = 0 to 23 when x = 1a, 2a.
(5) i in clki, dei, vsynci, hsynci and fldi = 0 or 1.
Figure 5-16. Video Input Ports clock signal
Figure 5-17. Video Input Ports timings