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AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Specifications Copyright © 2016–2017, Texas Instruments Incorporated
Table 5-29. Modes Summary (continued)
Virtual or Manual IO Mode Name Data Manual Timing Mode
VIP_MANUAL4 VIN2B (IOSET7/8/9) Rise-Edge Capture Mode Timings
VIP_MANUAL5 VIN2A (IOSET4/5/6) Fall-Edge Capture Mode Timings
VIP_MANUAL6 VIN2B (IOSET7/8/9) Fall-Edge Capture Mode Timings
VIP_MANUAL7 VIN1A (IOSET2) and VIN2B (IOSET1/10) Rise-Edge Capture Mode Timings
VIP_MANUAL9 VIN1B (IOSET6/7) Rise-Edge Capture Mode Timings
VIP_MANUAL10 VIN2B (IOSET2/11) Rise-Edge Capture Mode Timings
VIP_MANUAL11 VIN2B (IOSET2/11) Fall-Edge Capture Mode Timings
VIP_MANUAL12 VIN1A (IOSET2) and VIN2B (IOSET1/10) Fall-Edge Capture Mode Timings
VIP_MANUAL14 VIN1B (IOSET6/7) Fall-Edge Capture Mode Timings
VIP_MANUAL15 VIN1A (IOSET8/9/10) Rise-Edge Capture Mode Timings
VIP_MANUAL16 VIN1A (IOSET8/9/10) Fall-Edge Capture Mode Timings
PRU-ICSS
No Virtual or Manual IO Timing Mode Required All PRU_ICSS Modes not covered below
PR1_PRU1_DIR_IN_MANUAL PRU-ICSS1 PRU1 Direct Input Mode Timings
PR1_PRU1_DIR_OUT_MANUAL PRU-ICSS1 PRU1 Direct Output Mode Timings
PR1_PRU1_PAR_CAP_MANUAL PRU-ICSS1 PRU1 Parallel Capture Mode Timings
PR2_PRU0_DIR_IN_MANUAL2 PRU-ICSS2 PRU0 IOSET2 Direct Input Mode Timings
PR2_PRU0_DIR_OUT_MANUAL2 PRU-ICSS2 PRU0 IOSET2 Direct Output Mode Timings
PR2_PRU1_DIR_IN_MANUAL1 PRU-ICSS2 PRU1 IOSET1 Direct Input Mode Timings
PR2_PRU1_DIR_IN_MANUAL2 PRU-ICSS2 PRU1 IOSET2 Direct Input Mode Timings
PR2_PRU1_DIR_OUT_MANUAL1 PRU-ICSS2 PRU1 IOSET1 Direct Output Mode Timings
PR2_PRU1_DIR_OUT_MANUAL2 PRU-ICSS2 PRU1 IOSET2 Direct Output Mode Timings
PR2_PRU0_PAR_CAP_MANUAL2 PRU-ICSS2 PRU0 IOSET2 Parallel Capture Mode Timings
PR2_PRU1_PAR_CAP_MANUAL1 PRU-ICSS2 PRU1 IOSET1 Parallel Capture Mode Timings
PR2_PRU1_PAR_CAP_MANUAL2 PRU-ICSS2 PRU1 IOSET2 Parallel Capture Mode Timings
HDMI, EMIF, Timers, I2C, HDQ/1-Wire, UART, McSPI, USB, PCIe, DCAN, GPIO, KBD, PWM, JTAG, TPIU, SDMA, INTC
No Virtual or Manual IO Timing Mode Required All Modes
5.9.6.3 VIP
The Device includes 1 Video Input Ports (VIP).
Table 5-30, Figure 5-16 and Figure 5-17 present timings and switching characteristics of the VIPs.
CAUTION
The I/O timings provided in this section are valid only for VIN1 and VIN2 if
signals within a single IOSET are used. The IOSETs are defined in Table 5-31.
Table 5-30. Timing Requirements for VIP
(3)(4)(5)
NO. PARAMETER DESCRIPTION MIN MAX UNIT
V1 t
c(CLK)
Cycle time, vinx_clki
(3) (5)
6.06
(2)
ns
V2 t
w(CLKH)
Pulse duration, vinx_clki high
(3) (5)
0.45 × P
(2)
ns
V3 t
w(CLKL)
Pulse duration, vinx_clki low
(3) (5)
0.45 × P
(2)
ns
V4 t
su(CTL/DATA-CLK)
Input setup time, Control (vinx_dei, vinx_vsynci, vinx_fldi,
vinx_hsynci) and Data (vinx_dn) valid to vinx_clki transition
(3) (4) (5)
3.11
(2)
ns