165
AM5706, AM5708
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SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
Table 5-26. DPLL Type A Characteristics (continued)
NAME DESCRIPTION MIN TYP MAX UNIT COMMENTS
f
CLKOUTHIF
CLKOUTHIF output frequency
20
(3)
1400
(4)
MHz F
INPHIF
/ M3 if clkinphifsel = 1
40
(3)
2200
(4)
MHz
2 × [M / (N + 1)] × F
INP
× [1 /
M3] if clkinphifsel = 0
f
CLKDCOLDO
DCOCLKLDO output
frequency
40 2800 MHz
2 × [M / (N + 1)] × F
INP
(in
locked condition)
t
lock
Frequency lock time
6 + 350 ×
REFCLK
µs
p
lock
Phase lock time
6 + 500 ×
REFCLK
µs
t
relock-L
Relock time—Frequency
lock
(5)
(LP relock time from
bypass)
6 + 70 ×
REFCLK
µs
DPLL in LP relock time:
lowcurrstdby = 1
p
relock-L
Relock time—Phase lock
(5)
(LP relock time from bypass)
6 + 120 ×
REFCLK
µs
DPLL in LP relock time:
lowcurrstdby = 1
t
relock-F
Relock time—Frequency
lock
(5)
(fast relock time from
bypass)
3.55 + 70 ×
REFCLK
µs
DPLL in fast relock time:
lowcurrstdby = 0
p
relock-F
Relock time—Phase lock
(5)
(fast relock time from bypass)
3.55 + 120 ×
REFCLK
µs
DPLL in fast relock time:
lowcurrstdby = 0
(1) The minimum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
For M2 > 1, the minimum frequency on these clocks will further scale down by factor of M2.
(2) The maximum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
(3) The minimum frequency on CLKOUTHIF is assuming M3 = 1. For M3 > 1, the minimum frequency on this clock will further scale down
by factor of M3.
(4) The maximum frequency on CLKOUTHIF is assuming M3 = 1.
(5) Relock time assumes typical operating conditions, 10°C maximum temperature drift.
(6) Bypass mode: f
CLKOUT
= F
INP
if ulowclken = 0. For more information, see the Device TRM.
Table 5-27. DPLL Type B Characteristics
NAME DESCRIPTION MIN TYP MAX UNIT COMMENTS
f
input
CLKINP input clock frequency 0.62 60 MHz F
INP
f
internal
REFCLK internal reference
clock frequency
0.62 2.5 MHz [1 / (N + 1)] × F
INP
f
CLKINPULOW
CLKINPULOW bypass input
clock frequency
0.001 600 MHz
Bypass mode: f
CLKOUT
=
f
CLKINPULOW
/ (M1 + 1) If
ulowclken = 1
(4)
f
CLKLDOOUT
CLKOUTLDO output clock
frequency
20
(1)(5)
2500
(2)(5)
MHz
M / (N + 1)] × F
INP
× [1 / M2]
(in locked condition)
f
CLKOUT
CLKOUT output clock
frequency
20
(1)(5)
1450
(2)(5)
MHz
[M / (N + 1)] × F
INP
× [1 / M2]
(in locked condition)
f
CLKDCOLDO
Internal oscillator (DCO) output
clock frequency
750
(5)
1500
(5)
MHz
[M / (N + 1)] × F
INP
(in locked
condition)
1250
(5)
2500
(5)
MHz
t
J
CLKOUTLDO period jitter
–2.5% 2.5%
The period jitter at the output
clocks is ± 2.5% peak to peak
CLKOUT period jitter
CLKDCOLDO period jitter
t
lock
Frequency lock time
350 ×
REFCLKs
µs
p
lock
Phase lock time
500 ×
REFCLKs
µs
t
relock-L
Relock time—Frequency lock
(3)
(LP relock time from bypass)
9 + 30 ×
REFCLKs
µs
p
relock-L
Relock time—Phase lock
(3)
(LP
relock time from bypass)
9 + 125 ×
REFCLKs
µs