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AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Specifications Copyright © 2016–2017, Texas Instruments Incorporated
5.9.4.3.1 DPLL Characteristics
The DPLL has three relevant input clocks. One of them is the reference clock (CLKINP) used to generated
the synthesized clock but can also be used as the bypass clock whenever the DPLL enters a bypass
mode. It is therefore mandatory. The second one is a fast bypass clock (CLKINPULOW) used when
selected as the bypass clock and is optional. The third clock (CLKINPHIF) is explained in the next
paragraph.
The DPLL has three output clocks (namely CLKOUT, CLKOUTX2, and CLKOUTHIF). CLKOUT and
CLKOUTX2 run at the bypass frequency whenever the DPLL enters a bypass mode. Both of them are
generated from the lock frequency divided by a post-divider (namely M2 post-divider). The third clock,
CLKOUTHIF, has no automatic bypass capability. It is an output of a post-divider (M3 post-divider) with
the input clock selectable between the internal lock clock (Fdpll) and CLKINPHIF input of the PLL through
an asynchronous multplexing.
For more information, see the Power Reset Controller Management chapter of the Device TRM.
Table 5-25 summarizes DPLL type described in Section 5.9.4.3, DPLLs, DLLs Specifications introduction.
Table 5-25. DPLL Control Type
DPLL NAME TYPE CONTROLLED BY PRCM
DPLL_ABE Table 5-26 (Type A) Yes
(1)
DPLL_CORE Table 5-26 (Type A) Yes
(1)
DPLL_DEBUGSS Table 5-26 (Type A) No
(2)
DPLL_DSP Table 5-26 (Type A) Yes
(1)
DPLL_GMAC Table 5-26 (Type A) Yes
(1)
DPLL_HDMI Table 5-27 (Type B) No
(2)
DPLL_IVA Table 5-26 (Type A) Yes
(1)
DPLL_MPU Table 5-26 (Type A) Yes
(1)
DPLL_PER Table 5-26 (Type A) Yes
(1)
APLL_PCIE Table 5-26 (Type A) Yes
(1)
DPLL_PCIE_REF Table 5-27 (Type B) Yes
(1)
DPLL_USB Table 5-27 (Type B) Yes
(1)
DPLL_USB_OTG_SS Table 5-27 (Type B) No
(2)
DPLL_VIDEO1 Table 5-26 (Type A) No
(2)
DPLL_DDR Table 5-26 (Type A) Yes
(1)
DPLL_GPU Table 5-26 (Type A) Yes
(1)
(1) DPLL is in the always-on domain.
(2) DPLL is not controlled by the PRCM.
Table 5-26 and Table 5-27 summarize the DPLL characteristics and assume testing over recommended
operating conditions.
Table 5-26. DPLL Type A Characteristics
NAME DESCRIPTION MIN TYP MAX UNIT COMMENTS
f
input
CLKINP input frequency 0.032 52 MHz F
INP
f
internal
Internal reference frequency 0.15 52 MHz REFCLK
f
CLKINPHIF
CLKINPHIF input frequency 10 1400 MHz F
INPHIF
f
CLKINPULOW
CLKINPULOW input frequency 0.001 600 MHz
Bypass mode: f
CLKOUT
=
f
CLKINPULOW
/ (M1 + 1) if
ulowclken = 1
(6)
f
CLKOUT
CLKOUT output frequency 20
(1)
1400
(2)
MHz
[M / (N + 1)] × F
INP
× [1 / M2]
(in locked condition)
f
CLKOUTx2
CLKOUTx2 output frequency 40
(1)
2200
(2)
MHz
2 × [M / (N + 1)] × F
INP
× [1 /
M2] (in locked condition)