xi_osc1
CK0 CK1 CK1
SPRS906_CLK_08
162
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Specifications Copyright © 2016–2017, Texas Instruments Incorporated
(1) Period jitter is meant here as follows:
– The maximum value is the difference between the longest measured clock period and the expected clock period
– The minimum value is the difference between the shortest measured clock period and the expected clock period
(2) Crystal characteristics should account for tolerance+stability+aging.
(3) The Period jitter requirement for osc1 can be relaxed to 0.02 × tc(xiosc1) under the following constraints:
a.The osc1/SYS_CLK2 clock bypasses all device PLLs
b.The osc1/SYS_CLK2 clock is only used to source the DSS pixel clock outputs
Figure 5-15. xi_osc1 Input Clock
5.9.4.1.4 RC On-die Oscillator Clock
NOTE
The OSC_32K_CLK clock, provided by the On-die 32K RC oscillator, inside of the SoC, is
not accurate 32kHz clock.
The frequency may significantly vary with temperature and silicon characteristics.
For more information about OSC_32K_CLK see the Device TRM, Chapter: Power, Reset, and Clock
Management.
5.9.4.2 Output Clocks
The device provides three output clocks. Summary of these output clocks are as follows:
• clkout1 - Device Clock output 1. Can be used as a system clock for other devices. The source of the
clkout1 could be either:
– The input system clock and alternate clock (xi_osc0 or xi_osc1)
– CORE clock (from CORE output)
– 192-MHz clock (from PER DPLL output)
• clkout2 - Device Clock output 2. Can be used as a system clock for other devices. The source of the
clkout2 could be either:
– The input system clock and alternate clock (xi_osc0 or xi_osc1)
– CORE clock (from CORE output)
– 192-MHz clock (from PER DPLL output)
• clkout3 - Device Clock output 3. Can be used as a system clock for other devices. The source of the
clkout3 could be either:
– The input system clock and alternate clock (xi_osc0 or xi_osc1)
– CORE clock (from CORE output)
– 192-MHz clock (from PER DPLL output)
For more information about Output Clocks see Device TRM, Chapter: Power, Reset, and Clock
Management.