xi_osc1
vssa_osc1
Device
xo_osc1
C
f1
Crystal
Rd
C
f2
(Optional)
Rd
(Optional)
xi_osc0
CK0 CK1 CK1
SPRS906_CLK_05
159
AM5706, AM5708
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SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
Table 5-20 details the OSC0 input clock timing requirements.
Table 5-20. OSC0 Input Clock Timing Requirements
NAME DESCRIPTION MIN TYP MAX UNIT
CK0
1 /
t
c(xiosc0)
Frequency, xi_osc0 19.2, 20, 27 MHz
CK1 t
w(xiosc0)
Pulse duration, xi_osc0 low or high
0.45 ×
t
c(xiosc0)
0.55 ×
t
c(xiosc0)
ns
t
j(xiosc0)
Period jitter
(1)
, xi_osc0
0.01 ×
t
c(xiosc0)
ns
t
R(xiosc0)
Rise time, xi_osc0 5 ns
t
F(xiosc0)
Fall time, xi_osc0 5 ns
t
j(xiosc0)
Frequency accuracy
(2)
, xi_osc0
Ethernet and MLB not used ±200
ppm
Ethernet RGMII and RMII
using derived clock
±50
Ethernet MII using derived
clock
±100
(1) Period jitter is meant here as follows:
– The maximum value is the difference between the longest measured clock period and the expected clock period
– The minimum value is the difference between the shortest measured clock period and the expected clock period
(2) Crystal characteristics should account for tolerance+stability+aging.
Figure 5-11. xi_osc0 Input Clock
5.9.4.1.3 Auxiliary Oscillator OSC1 Input Clock
SYS_CLKIN2 is received directly from oscillator OSC1. For more information about SYS_CLKIN2 see
Device TRM, Chapter: Power, Reset, and Clock Management.
5.9.4.1.3.1 OSC1 External Crystal
An external crystal is connected to the device pins. Figure 5-12 describes the crystal implementation.
Figure 5-12. Crystal Implementation