DEVICE
clkout1
To quartz (from oscillator output).
resetn
rstoutn
External Reference Clock [3:0].
For Audio and other Peripherals
xref_clk1
sysboot[15:0]
From quartz (19.2, 20 or 27 MHz)
or from CMOS square clock source (19.2, 20 or 27MHz).
Boot Mode Configuration
xi_osc1
Warm reset output.
Device reset input.
porz
Power ON Reset.
xi_osc0
xo_osc0
xo_osc1
From quartz (range from MHz)
or from CMOS square clock source(range from MHz).
19.2 to 32
12 to 38.4
To quartz (from oscillator output).
clkout2
clkout3
xref_clk0
xref_clk2
xref_clk3
Output clkout[3:1] clocks come from:
• Either the input system clock and alternate clock (xi_osc0 or xi_osc1)
• Or a CORE clock (from CORE output)
• Or a 192-MHz clock (from PER DPLL output).
156
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Specifications Copyright © 2016–2017, Texas Instruments Incorporated
Figure 5-7. Clock Interface
5.9.4.1 Input Clocks / Oscillators
• The source of the internal system clock (SYS_CLK1) could be either:
– A CMOS clock that enters on the xi_osc0 ball (with xo_osc0 left unconnected on the CMOS clock
case).
– A crystal oscillator clock managed by xi_osc0 and xo_osc0.
• The source of the internal system clock (SYS_CLK2) could be either:
– A CMOS clock that enters on the xi_osc1 ball (with xo_osc1 left unconnected on the CMOS clock
case).
– A crystal oscillator clock managed by xi_osc1 and xo_osc1.
SYS_CLKIN1 is received directly from oscillator OSC0. For more information about SYS_CLKIN1 see
Device TRM, Chapter: Power, Reset, and Clock Management.
5.9.4.1.1 OSC0 External Crystal
An external crystal is connected to the device pins. Figure 5-8 describes the crystal implementation.