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AM5706, AM5708
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SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
Table 4-1. Pin Attributes
(1)
(continued)
BALL NUMBER
[1]
BALL NAME [2] SIGNAL NAME [3] PN [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
RESET
REL.
STATE [8]
BALL
RESET
REL.
MUXMODE
[9]
I/O
VOLTAGE
VALUE
[10]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
DSIS [15]
AB16 ddr1_ba2 ddr1_ba2 0 O PU drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AC19 ddr1_csn0 ddr1_csn0 0 O PU drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AA23 ddr1_d0 ddr1_d0 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AC24 ddr1_d1 ddr1_d1 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AB24 ddr1_d2 ddr1_d2 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AD24 ddr1_d3 ddr1_d3 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AB23 ddr1_d4 ddr1_d4 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AC23 ddr1_d5 ddr1_d5 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AD23 ddr1_d6 ddr1_d6 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AE24 ddr1_d7 ddr1_d7 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AA24 ddr1_d8 ddr1_d8 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
W25 ddr1_d9 ddr1_d9 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
Y23 ddr1_d10 ddr1_d10 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AD25 ddr1_d11 ddr1_d11 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AC25 ddr1_d12 ddr1_d12 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AB25 ddr1_d13 ddr1_d13 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AA25 ddr1_d14 ddr1_d14 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
W24 ddr1_d15 ddr1_d15 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
W23 ddr1_d16 ddr1_d16 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
U25 ddr1_d17 ddr1_d17 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
U24 ddr1_d18 ddr1_d18 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
W21 ddr1_d19 ddr1_d19 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
T22 ddr1_d20 ddr1_d20 0 IO PD PD 1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy