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AM5706, AM5708
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SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
Table 5-9. IQ1833 Buffers DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN NOM MAX UNIT
1.8-V Mode
V
IH
Input high-level threshold (Does not meet JEDEC V
IH
) 0.75 ×
VDDS
V
V
IL
Input low-level threshold (Does not meet JEDEC V
IL
) 0.25 ×
VDDS
V
V
HYS
Input hysteresis voltage 100 mV
I
IN
Input current at each I/O pin 2 11 µA
C
PAD
Pad capacitance (including package capacitance) 1 pF
3.3-V Mode
V
IH
Input high-level threshold (Does not meet JEDEC V
IH
) 2.0 V
V
IL
Input low-level threshold (Does not meet JEDEC V
IL
) 0.6 V
V
HYS
Input hysteresis voltage 400 mV
I
IN
Input current at each I/O pin 5 11 µA
C
PAD
Pad capacitance (including package capacitance) 1 pF
(1) VDDS in this table stands for corresponding power supply (i.e. vddshv3). For more information on the power supply name and the
corresponding ball, see Table 4-1, POWER [11] column.
Table 5-10. IHHV1833 Buffers DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN NOM MAX UNIT
Signal Names in MUXMODE 0: porz / wakeup3 / wakeup0;
Balls: AB10/AC10/F19;
1.8-V Mode
V
IH
Input high-level threshold 1.2
(1)
V
V
IL
Input low-level threshold 0.4 V
V
HYS
Input hysteresis voltage 40 mV
I
IN
Input current at each I/O pin 0.02 1 µA
C
PAD
Pad capacitance (including package capacitance) 1 pF
3.3-V Mode
V
IH
Input high-level threshold 1.2
(1)
V
V
IL
Input low-level threshold 0.4 V
V
HYS
Input hysteresis voltage 40 mV
I
IN
Input current at each I/O pin 5 8 µA
C
PAD
Pad capacitance (including package capacitance) 1 pF
(1) The IHHV1833 buffer exists in the dual-voltage IO logic that can be powered by either 1.8V or 3.3V provided by vddshv3. However, the
vddshv3 supply is only used for input protection circuitry, not for logic functionality. The logic in this buffer operates entirely on the
vdds18v supply. Therefore, these input buffers are fully functional whenever vdds18v is valid.
Table 5-11. LVCMOS CSI2 DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN NOM MAX UNIT
Signals MUXMODE 0: csi2_0_dx[2:0]; csi2_0_dy[2:0];
Bottom Balls: AC1 / AB2 / AD1 / AC2 / AE2 / AD2
MIPI D-PHY Mode Low-Power Receiver (LP-RX)
V
IH
Input high-level voltage 880 1350 mV
V
IL
Input low-level voltage 550 mV
V
ITH
Input high-level threshold 880 mV
V
ITL
Input low-level threshold 550 mV
