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AM5706, AM5708
www.ti.com
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
Table 5-7. LVCMOS DDR DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN NOM MAX UNIT
V
CM
Input common-mode voltage VREF
-10%vdds
VREF+
10%vdds
V
C
PAD
Pad capacitance (including package capacitance) 3 pF
Differential Receiver Mode
V
SWING
Input voltage swing DDR3/DDR3L 0.2 vdds+0.4 V
V
CM
Input common-mode voltage VREF
-10%vdds
VREF+
10%vdds
V
C
PAD
Pad capacitance (including package capacitance) 3 pF
(1) VDDS in this table stands for corresponding power supply (i.e. vdds_ddr1). For more information on the power supply name and the
corresponding ball, see Table 4-1, POWER [11] column.
(2) VREF in this table stands for corresponding Reference Power Supply (i.e. ddr1_vref0). For more information on the power supply name
and the corresponding ball, see Table 4-1, POWER [11] column.
Table 5-8. Dual Voltage LVCMOS I
2
C DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN NOM MAX UNIT
Signal Names in MUXMODE 0: i2c1_scl; i2c1_sda; i2c2_scl; i2c2_sda;
Balls: G22 / G23 / G21 / F23
I
2
C Standard Mode – 1.8 V
V
IH
Input high-level threshold 0.7 × VDDS V
V
IL
Input low-level threshold 0.3 × VDDS V
V
hys
Hysteresis 0.1 × VDDS V
I
IN
Input current at each I/O pin with an input voltage
between 0.1 × VDDS to 0.9 × VDDS
12 µA
I
OZ
I
OZ
(I
PAD
Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
PAD is swept from 0 to VDDS and the Max(I
(PAD)
)
is measured and is reported as I
OZ
12 µA
C
IN
Input capacitance 10 pF
V
OL3
Output low-level threshold open-drain at 3-mA
sink current
0.2 × VDDS V
I
OLmin
Low-level output current @V
OL
=0.2 × VDDS 3 mA
t
OF
Output fall time from V
IHmin
to V
ILmax
with a bus
capacitance CB from 5 pF to 400 pF
250 ns
I
2
C Fast Mode – 1.8 V
V
IH
Input high-level threshold 0.7 × VDDS V
V
IL
Input low-level threshold 0.3 × VDDS V
V
hys
Hysteresis 0.1 × VDDS V
I
IN
Input current at each I/O pin with an input voltage
between 0.1 × VDDS to 0.9 × VDDS
12 µA
I
OZ
I
OZ
(I
PAD
Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
PAD is swept from 0 to VDDS and the Max(I
(PAD)
)
is measured and is reported as I
OZ
12 µA
C
IN
Input capacitance 10 pF
V
OL3
Output low-level threshold open-drain at 3-mA
sink current
0.2 × VDDS V
I
OLmin
Low-level output current @V
OL
=0.2 × VDDS 3 mA
t
OF
Output fall time from V
IHmin
to V
ILmax
with a bus
capacitance CB from 10 pF to 400 pF
20+0.1 × Cb 250 ns