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AM5706, AM5708
www.ti.com
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
Table 5-6. Maximum Supported Frequency (continued)
Module Clock Sources
Instance Name Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
USB2 USB2_MICLK Int 266 L3INIT_L3_GICLK CORE_X2_CLK DPLL_CORE
USB2PHY2_TREF_
CLK
Func 38.4 USB_OTG_SS_REF_C
LK
SYS_CLK1 OSC0
USB2PHY2_REF_C
LK
Func 960 L3INIT_960M_GFCLK L3INIT_960_GFCL
K
DPLL_USB
USB_PHY1_CORE USB2PHY1_WKUP_
CLK
Func 0.032 COREAON_32K_GFCL
K
SYS_CLK1/610 OSC0
USB_PHY2_CORE USB2PHY2_WKUP_
CLK
Func 0.032 COREAON_32K_GFCL
K
SYS_CLK1/610 OSC0
VIP1 L3_CLK_PROC_CL
K
Int &
Func
266 VIP1_GCLK CORE_X2_CLK DPLL_CORE
CORE_ISS_MAIN_
CLK
DPLL_CORE
VPE L3_CLK_PROC_CL
K
Int &
Func
300 VPE_GCLK CORE_ISS_MAIN_
CLK
DPLL_CORE
VIDEO1_CLKOUT
4
DPLL_VIDEO1
WD_TIMER1 PIOCPCLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
PITIMERCLK Func 0.032 OSC_32K_CLK RC_CLK RC oscillator
WD_TIMER2 WD_TIMER2_ICLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
WD_TIMER2_FCLK Func 0.032 WKUPAON_SYS_GFC
LK
WKUPAON_32K_
GFCLK
5.6 Power Consumption Summary
NOTE
Maximum power consumption for this SoC depends on the specific use conditions for the
end system. Contact your TI representative for assistance in estimating maximum power
consumption for the end system use case.
5.7 Electrical Characteristics
NOTE
The data specified in Section 5.7 through Section 5.7.3 are subject to change.
NOTE
The interfaces or signals described in Section 5.7 through Section 5.7.3 correspond to the
interfaces or signals available in multiplexing mode 0 (Function 1).
All interfaces or signals multiplexed on the balls described in these tables have the same DC
electrical characteristics, unless multiplexing involves a PHY/GPIO combination in which
case different DC electrical characteristics are specified for the different multiplexing modes
(Functions).