Copyright © 2016–2017, Texas Instruments IncorporatedTerminal Configuration and Functions
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Product Folder Links: AM5706 AM5708
14
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Table 4-1. Pin Attributes
(1)
(continued)
BALL NUMBER
[1]
BALL NAME [2] SIGNAL NAME [3] PN [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
RESET
REL.
STATE [8]
BALL
RESET
REL.
MUXMODE
[9]
I/O
VOLTAGE
VALUE
[10]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
DSIS [15]
AB18 ddr1_cke ddr1_cke 0 O PU drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AE21 ddr1_nck ddr1_nck 0 O PU drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AD17 ddr1_rasn ddr1_rasn 0 O PU drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AE17 ddr1_rst ddr1_rst 0 O PD drive 0
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AE18 ddr1_wen ddr1_wen 0 O PU drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AC18 ddr1_a0 ddr1_a0 0 O PD drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AE19 ddr1_a1 ddr1_a1 0 O PD drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AD19 ddr1_a2 ddr1_a2 0 O PD drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AB19 ddr1_a3 ddr1_a3 0 O PD drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AD20 ddr1_a4 ddr1_a4 0 O PD drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AE20 ddr1_a5 ddr1_a5 0 O PD drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AA18 ddr1_a6 ddr1_a6 0 O PD drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AA20 ddr1_a7 ddr1_a7 0 O PD drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
Y21 ddr1_a8 ddr1_a8 0 O PD drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AC20 ddr1_a9 ddr1_a9 0 O PD drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AA21 ddr1_a10 ddr1_a10 0 O PD drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AC21 ddr1_a11 ddr1_a11 0 O PD drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AC22 ddr1_a12 ddr1_a12 0 O PD drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AC15 ddr1_a13 ddr1_a13 0 O PD drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AB15 ddr1_a14 ddr1_a14 0 O PD drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AC16 ddr1_a15 ddr1_a15 0 O PD drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AE16 ddr1_ba0 ddr1_ba0 0 O PU drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AA16 ddr1_ba1 ddr1_ba1 0 O PU drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy