138
AM5706, AM5708
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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Specifications Copyright © 2016–2017, Texas Instruments Incorporated
Table 5-6. Maximum Supported Frequency (continued)
Module Clock Sources
Instance Name Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
TIMER9 TIMER9_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER9_FCLK Func 100 TIMER9_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
TIMER10 TIMER10_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER10_FCLK Func 100 TIMER10_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
TIMER11 TIMER11_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
TIMER11_FCLK Func 100 TIMER11_GFCLK SYS_CLK1 OSC0
FUNC_32K_CLK OSC0
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
DPLL_ABE_X2_CL
K
DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
TIMER12 TIMER12_ICLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
TIMER12_FCLK Func 0.032 OSC_32K_CLK RC_CLK RC oscillator