Copyright © 2016–2017, Texas Instruments Incorporated Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links: AM5706 AM5708
13
AM5706, AM5708
www.ti.com
SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
Table 4-1. Pin Attributes
(1)
BALL NUMBER
[1]
BALL NAME [2] SIGNAL NAME [3] PN [4]
MUXMODE
[5]
TYPE [6]
BALL
RESET
STATE [7]
BALL
RESET
REL.
STATE [8]
BALL
RESET
REL.
MUXMODE
[9]
I/O
VOLTAGE
VALUE
[10]
POWER
[11]
HYS [12]
BUFFER
TYPE [13]
PULL
UP/DOWN
TYPE [14]
DSIS [15]
F8 cap_vbbldo_dsp cap_vbbldo_dsp CAP
T7 cap_vbbldo_gpu cap_vbbldo_gpu CAP
G14 cap_vbbldo_iva cap_vbbldo_iva CAP
F17 cap_vbbldo_mpu cap_vbbldo_mpu CAP
U20 cap_vddram_core1 cap_vddram_core1 CAP
K7 cap_vddram_core3 cap_vddram_core3 CAP
G19 cap_vddram_core4 cap_vddram_core4 CAP
L7 cap_vddram_dsp cap_vddram_dsp CAP
V7 cap_vddram_gpu cap_vddram_gpu CAP
G12 cap_vddram_iva cap_vddram_iva CAP
G18 cap_vddram_mpu cap_vddram_mpu CAP
AC1 csi2_0_dx0 csi2_0_dx0 0 I 1.8 Yes LVCMOS
CSI2
PU/PD
AD1 csi2_0_dx1 csi2_0_dx1 0 I 1.8 Yes LVCMOS
CSI2
PU/PD
AE2 csi2_0_dx2 csi2_0_dx2 0 I 1.8 Yes LVCMOS
CSI2
PU/PD
AB2 csi2_0_dy0 csi2_0_dy0 0 I 1.8 Yes LVCMOS
CSI2
PU/PD
AC2 csi2_0_dy1 csi2_0_dy1 0 I 1.8 Yes LVCMOS
CSI2
PU/PD
AD2 csi2_0_dy2 csi2_0_dy2 0 I 1.8 Yes LVCMOS
CSI2
PU/PD
H23 dcan1_rx dcan1_rx 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual
Voltage
LVCMOS
PU/PD 1
uart8_txd 2 O
mmc2_sdwp 3 I 0
hdmi1_cec No 6 IO
gpio1_15 14 IO
Driver off 15 I
H22 dcan1_tx dcan1_tx 0 IO PU PU 15 1.8/3.3 vddshv3 Yes Dual
Voltage
LVCMOS
PU/PD 1
uart8_rxd 2 I 1
mmc2_sdcd 3 I 1
hdmi1_hpd No 6 IO
gpio1_14 14 IO
Driver off 15 I
AD16 ddr1_casn ddr1_casn 0 O PU drive 1
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy
AD21 ddr1_ck ddr1_ck 0 O PD drive 0
(OFF)
1.35/1.5 vdds_ddr1 No LVCMOS
DDR
PUx/PDy