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AM5706, AM5708
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SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
Table 5-6. Maximum Supported Frequency (continued)
Module Clock Sources
Instance Name Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
McASP2 MCASP2_AHCLKR Func 100 MCASP2_AHCLKR ABE_24M_GFCLK DPLL_ABE
ABE_SYS_CLK OSC0
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0 Module ATL
ATL_CLK1 Module ATL
ATL_CLK2 Module ATL
ATL_CLK3 Module ATL
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
MLB_CLK Module MLB
MLBP_CLK Module MLB
MCASP2_AHCLKX Func 100 MCASP2_AHCLKX ABE_24M_GFCLK DPLL_ABE
ABE_SYS_CLK OSC0
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0 Module ATL
ATL_CLK1 Module ATL
ATL_CLK2 Module ATL
ATL_CLK3 Module ATL
SYS_CLK2 OSC1
XREF_CLK0 XREF_CLK0
XREF_CLK1 XREF_CLK1
XREF_CLK2 XREF_CLK2
XREF_CLK3 XREF_CLK3
MLB_CLK Module MLB
MLBP_CLK Module MLB
MCASP2_FCLK Func 192 MCASP2_AUX_GFCLK PER_ABE_X1_GF
CLK
DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
MCASP2_ICLK Int 266 L4PER2_L3_GICLK CORE_X2_CLK DPLL_CORE