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AM5706, AM5708
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SPRS961B –AUGUST 2016–REVISED SEPTEMBER 2017
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SpecificationsCopyright © 2016–2017, Texas Instruments Incorporated
Table 5-6. Maximum Supported Frequency (continued)
Module Clock Sources
Instance Name Input Clock Name
Clock
Type
Max. Clock
Allowed (MHz)
PRCM Clock Name
PLL / OSC /
Source Clock
Name
PLL / OSC /
Source Name
DSS DISPC LCD1_CLK Func 209.3 N/A DPLL_DSI1_A_CL
K1
See DSS data in
the rows above
DSS_CLK
LCD2_CLK Func 209.3 N/A DPLL_DSI1_B_CL
K1
DSS_CLK
LCD3_CLK Func 209.3 N/A DPLL_DSI1_C_CL
K1
DSS_CLK
F_CLK Func 209.3 N/A DPLL_DSI1_A_CL
K1
DPLL_DSI1_B_CL
K1
DPLL_DSI1_C_CL
K1
DSS_CLK
DPLL_HDMI_CLK1
EFUSE_CTRL_CU
ST
ocp_clk Int 133 CUSTEFUSE_L4_GICL
K
CORE_X2_CLK DPLL_CORE
sys_clk Func 38.4 CUSTEFUSE_SYS_GF
CLK
SYS_CLK1 OSC0
ELM ELM_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
EMIF_OCP_FW L3_CLK Int 266 EMIF_L3_GICLK CORE_X2_CLK DPLL_CORE
EMIF_PHY1 EMIF_PHY1_FCLK Func DDR EMIF_PHY_GCLK EMIF_PHY_GCLK DPLL_DDR
EMIF1 EMIF1_ICLK Int 266 EMIF_L3_GICLK CORE_X2_CLK DPLL_CORE
GMAC_SW CPTS_RFT_CLK Func 266 GMAC_RFT_CLK PER_ABE_X1_GF
CLK
DPLL_ABE
VIDEO1_CLK DPLL_VIDEO1
HDMI_CLK DPLL_HDMI
CORE_X2_CLK DPLL_CORE
MAIN_CLK Int 125 GMAC_MAIN_CLK GMAC_250M_CLK DPLL_GMAC
MHZ_250_CLK Func 250 GMII_250MHZ_CLK GMII_250MHZ_CL
K
DPLL_GMAC
MHZ_5_CLK Func 5 RGMII_5MHZ_CLK GMAC_RMII_HS_
CLK
DPLL_GMAC
MHZ_50_CLK Func 50 RMII_50MHZ_CLK GMAC_RMII_HS_
CLK
DPLL_GMAC
RMII1_MHZ_50_CL
K
Func 50 RMII_50MHZ_CLK GMAC_RMII_HS_
CLK
DPLL_GMAC
RMII2_MHZ_50_CL
K
Func 50 RMII_50MHZ_CLK GMAC_RMII_HS_
CLK
DPLL_GMAC
GPIO1 GPIO1_ICLK Int 38.4 WKUPAON_GICLK SYS_CLK1 OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
GPIO1_DBCLK Func 0.032 WKUPAON_SYS_GFC
LK
WKUPAON_32K_
GFCLK
OSC0
GPIO2 GPIO2_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
GPIO2_DBCLK Func 0.032 GPIO_GFCLK FUNC_32K_CLK OSC0
GPIO3 GPIO3_ICLK Int 266 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE
GPIO3_DBCLK Func 0.032 GPIO_GFCLK FUNC_32K_CLK OSC0