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AM5706BCBDDEA

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型号: AM5706BCBDDEA
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功能描述: Sitara Processors
PDF文件大小: 4339.62 Kbytes
PDF页数: 共392页
制造商: TI1[TI store]
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制造商网址: http://www.ti.com
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120%
ADVANCEINFORMATION
122
AM5706, AM5708
SPRS961B AUGUST 2016REVISED SEPTEMBER 2017
www.ti.com
Submit Documentation Feedback
Product Folder Links: AM5706 AM5708
Specifications Copyright © 2016–2017, Texas Instruments Incorporated
CAUTION
The OPP voltage and frequency values may change following the silicon
characterization result.
Table 5-2 describes the maximum supported frequency per speed grade for AM570x devices.
Table 5-2. Speed Grade Maximum Frequency
(1)(2)
Device Speed
Maximum frequency (MHz)
MPU DSP IPU IVA GPU L3 DDR3 / DDR3L
D 500 500 212.8 N/A N/A 266 667 (DDR3-1333)
J 1000 750 212.8 532 425 266 667 (DDR3-1333)
(1) N/A in this table stands for Not Applicable.
(2) If the corresponding core is not available in the respective subdevice, the value shall be read as N/A. For more information, see Table 3-
1, Device Comparison.
5.5.1 AVS and ABB Requirements
Adaptive Voltage Scaling (AVS) and Adaptive Body Biasing (ABB) are required on most of the vdd_*
supplies as defined in Table 5-3.
Table 5-3. AVS and ABB Requirements per vdd_* Supply
Supply AVS Required? ABB Required?
vdd Yes, for all OPPs No
vdd_dsp Yes, for all OPPs Yes, for all OPPs
5.5.2 Voltage And Core Clock Specifications
Table 5-4 shows the recommended OPP per voltage domain.
Table 5-4. Voltage Domains Operating Performance Points
(1)
DOMAIN CONDITION OPP_NOM OPP_HIGH
MIN
(3)
NOM
(2)
MAX
(3)
MIN
(3)
NOM
(2)
MAX DC
(4)
MAX
(3)
VD_CORE (V)
(8)
BOOT (Before AVS is
enabled)
(5)
1.11 1.15 1.2 Not Applicable
After AVS is enabled
(5)
AVS
Voltage
(6)
3.5%
AVS
Voltage
(6)
1.2 Not Applicable
VD_DSP (V)
(9)
BOOT (Before AVS is
enabled)
(5)
1.02 1.06 1.16 Not Applicable
After AVS is enabled
(5)
AVS
Voltage
(6)
3.5%
AVS
Voltage
(6)
1.2 AVS
Voltage
(6)
3.5%
AVS
Voltage
(6)
AVS
Voltage
(6)
+2%
AVS
Voltage
(6)
+ 5%
(1) The voltage ranges in this table are preliminary, and final voltage ranges may be different than shown. Systems should be designed with
the ability to modify the voltage to comply with future recommendations.
(2) In a typical implementation, the power supply should target the NOM voltage.
(3) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.
(4) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH
(Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.
(5) For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power-On-Hours), and device power.
(6) The AVS voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the
STD_FUSE_OPP Registers. For information about STD_FUSE_OPP Registers address, please refer to Control Module Section of the
TRM. The power supply should be adjustable over the following ranges for each required OPP:
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