8 Am49DL640BG March 8, 2002
PRELIMINARY
PIN DESCRIPTION
A20–A0 = 21 Address Inputs (Common)
A21, A-1 = 2 Addres s Inputs (Flash)
DQ15–DQ0 = 16 Data Inputs/Outputs (Common)
CE#f = Chip Enable (Flash)
CE1#s = Chip Enable 1 (pSRAM)
CE2s = Chip Enable 2 (pSRAM)
OE# = Output Enable (Comm on)
WE# = Write Enable (Common)
RY /BY # = Ready/B usy Output
UB#s = Upper Byte Control (pSRAM)
LB#s = Lower Byte Control (pSRAM)
CIOf = I/O Configuration (Flash)
CIOf = V
IH
= Word mode (x16),
CIOf = V
IL
= Byte mode (x8)
RESET# = Hardware Reset Pin, Active Low
WP#/ACC = Hardware Wr ite Protect/
Accelera t ion Pin (Fl ash)
V
CC
f = Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide f or
speed options and voltage supply
tolerances)
V
CC
s = pSRAM Power Supply
V
SS
= Device Ground (Common)
NC = Pin Not Connected Internally
LOGIC SYMBOL
21
16 or 8
DQ15–DQ0
A20–A0
CE#f
OE#
WE#
RESET#
UB#s
RY/BY#
WP#/ACC
SA
A21, A-1
LB#s
CIOf
CE1#s
CE2s
