58 Am49DL640BG March 8, 2002
PRELIMINARY
pSRAM DATA RET ENTION
Notes:
1. CE1#s ≥ V
CC
– 0.2 V, CE2s ≥ V
CC
– 0.2 V (CE1#s controlled) or CE2s ≤ 0.2 V (CE2s controlled).
2. Typical values are not 100% tested.
pSRAM POWER ON AND DEEP POWER DOWN
Figure 33. Deep Power-down Timing
Note: Data cannot be retained during deep power-down standby mode.
Figure 34. Power-on Timing
Parameter
Symbol
Parameter Description
Test Setup
Min Typ Max Unit
V
DR
V
CC
for Data Retention CS1#s ≥ V
CC
– 0.2 V (Note 1) 2.7 3.3 V
I
DR
Data Retention Current
V
CC
= 3.0 V, CE1#s ≥ V
CC
– 0.2 V
(Note 1)
1.0
(Note 2)
70 µA
t
CS
CE2 Setup Time 0 ns
t
CH
CE 2 Hold Time 300 µs
t
DPD
CE 2 Pulse Width 10 ms
t
CHC
CE2 Hold from CE#1 0 ns
t
CHP
CE 2 Hold from Power On 30 µs
CE#1
CE#2
t
DPD
t
CH
CE#1
V
DD
CE#2
t
CHC
t
CHP
t
CH
V
DD min
