4 Am49DL640BG March 8, 2002
PRELIMINARY
Latc hup C ha r a c t e r is tics . . . . . . . . . . . . . . . . . . . 57
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 57
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 57
pSRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 58
pSRAM Power on and Deep Power Down . . . . . 58
Figure 33. Deep Power-down Timing.............................................. 58
Figure 34. Power-on Timing............................................................ 58
pSRAM Address Skew . . . . . . . . . . . . . . . . . . . . . 59
Figure 35. Read Address Skew ..................................................... 59
Figure 36. Write Address Skew...................................................... 59
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 60
FLB073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............. 60
Revis ion Summary . . . . . . . . . . . . . . . . . . . . . . . . 61