March 8, 2002 Am49DL640BG 47
PRELIMINARY
FLASH AC CHARACTERISTICS
OE#
WE#
Addresses
t
OEH
t
DH
t
AHT
t
ASO
t
OEPH
t
OE
Valid Data
(first read) (second read) (stops toggling)
t
CEPH
t
AHT
t
AS
DQ6/DQ2 Valid Data
Valid
Status
Valid
Status
Valid
Status
RY/BY#
CE#f
Note: VA = Valid address; no t required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
Figure 23. Toggle Bit Timings (During Embedded Algorithms)
Note: DQ2 toggles only when read at an address within an erase-sus pended sector. The system may use OE# or CE#f to
toggle DQ2 and DQ6.
Figure 24. DQ2 vs. DQ6
Enter
Erase
Erase
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase Suspend
Read
Erase
WE#
DQ6
DQ2
Erase
Complete
Erase
Suspend
Suspend
Program
Resume
Embe dded
Erasing